三星nand命名规则
1. Memory (K)
2. NAND Flash : 9
3. Small Classification
(SLC : Single Level Cell, MLC : Multi Level Cell,
SM : SmartMedia, S/B : Small Block)
1 : SLC 1 Chip XD Card
2 : SLC 2 Chip XD Card
4 : SLC 4 Chip XD Card
A : SLC + Muxed I/ F Chip
B : Muxed I/ F Chip
D : SLC Dual SM
E : SLC DUAL (S/ B)
F : SLC Normal
G : MLC Normal
H : MLC QDP
J : Non-Muxed OneNand
K : SLC Die Stack
L : MLC DDP
M : MLC DSP
N : SLC DSP
Q : 4CHIP SM
R : SLC 4DIE STACK (S/ B)
S : SLC Single SM
T : SLC SINGLE (S/ B)
U : 2 STACK MSP
V : 4 STACK MSP
W : SLC 4 Die Stack
4~5. Density
12 : 512M
16 : 16M
28 : 128M
32 : 32M
40 : 4M
56 : 256M
64 : 64M
80 : 8M
1G : 1G
2G : 2G
4G : 4G
8G : 8G
AG : 16G
BG : 32G
CG : 64G
DG : 128G
00 : NONE
6~7. organization
00 : NONE
08 : x8
16 : x16
8. Vcc
A : 1.65V~3.6V
B : 2.7V (2.5V~2.9V)
C : 5.0V (4.5V~5.5V)
D : 2.65V (2.4V ~ 2.9V)
E : 2.3V~3.6V
R : 1.8V (1.65V~1.95V)
Q : 1.8V (1.7V ~ 1.95V)
T : 2.4V~3.0V
U : 2.7V~3.6V
V : 3.3V (3.0V~3.6V)
W : 2.7V~5.5V, 3.0V~5.5V
0 : NONE
9. Mode
0 : Normal
1 : Dual nCE & Dual R/ nB
4 : Quad nCE & Single R/ nB
5 : Quad nCE & Quad R/ nB
9 : 1st block OTP
A : Mask Option 1
L : Low grade
10. Generation
M : 1st Generation
A : 2nd Generation
B : 3rd Generation
C : 4th Generation
D : 5th Generation
11. "—"
12. Package
A : COB
B : TBGA
C : CHIP BIZ
D : 63-TBGA
E : TSOP1 (Lead-Free, 1217)
F : WSOP (Lead-Free)
G : FBGA
H : TBGA (Lead-Free)
I : ULGA (Lead-Free)
J : FBGA (Lead-Free)
K : TSOP1 (1217)
L : LGA
M : TLGA
N : TLGA2
P : TSOP1 (Lead-Free)
Q : TSOP2 (Lead-Free)
R : TSOP2-R
S : SMART MEDIA
T : TSOP2
U : COB (MMC)
V : WSOP
W : WAFER
Y : TSOP1
13. Temp
C : Commercial
I : Industrial
S : SmartMedia
B : SmartMedia BLUE
0 : NONE (Containing Wafer, CHIP, BIZ, Exception
handling code)
3 : Wafer Level 3
14. Bad Block
A : Apple Bad Block
B : Include Bad Block
D : Daisychain Sample
K : Sandisk Bin
L : 1~5 Bad Block
N : ini. 0 blk, add. 10 blk
S : All Good Block
0 : NONE (Containing Wafer, CHIP, BIZ, Exception
handling code)
15. NAND-Reserved
0 : Reserved
16. Packing Type
- Common to all products, except of Mask ROM
- Divided into TAPE & REEL(In Mask ROM, divided into TRAY, AMMO Packing Separately)
Hynix nand命名规则
H 2 7 X X X X X X X X X - X X
(1) HYNIX
(2) PRODUCT FAMILY
(4) POWER SUPPLY(VCC)
(8) NAND CLASSIFICATION
(7) ORGANIZATION
(14) BAD BLOCK
(11) PACKAGE TYPE
2 : Flash
S
A
B
F
G
H
J
K
T
U
V
W
Y
: SLC + Single Die + Small Block
: SLC + Double Die + Small Block
: SLC + Quadruple Die + Small Block
: SLC + Single Die + Large Block
: SLC + Double Die + Large Block
: SLC + Quadruple Die + Large Block
: SLC + ODP + Large Block
: SLC + DSP + Large Block
: MLC + Single Die + Large Block
: MLC + Double Die + Large Block
: MLC + Quadruple Die + Large Block
: MLC + DSP + Large Block
: MLC + ODP + Large Block
C
E
M
I
B
S
P
: Included Bad Block
: 1~5 Bad Block Included
: All Good Block
T
V
S
N
F
X
M
Y
U
W
C
K
D
: TSOP1
: WSOP
: USOP
: LSOP1
: FBGA
: LGA
: WLGA
: VLGA
: ULGA
: Wafer
: PGD1 (chip)
: KGD
: PGD2
: 1st
: 2nd
: 3rd
: 4th
M
A
B
C
(5), (6) DENSITY
1
2
4
5
D
F
: 1 nCE & 1 R/nB; Sequential Row Read Enable
: 1 nCE & 1 R/nB; Sequential Row Read Disable
: 2 nCE & 2 R/nB; Sequential Row Read Enable
: 2 nCE & 2 R/nB; Sequential Row Read Disable
: Dual Interface; Sequential Row Read Disable
: 4 nCE & 4 R/nB ; Sequential Row Read Disable
micron镁光nand命名规则
www.micron.com/support/designsupport/documents/png
Standard NAND Flash Part Numbering System
Micron's part numbering system is available at
Standard NAND Flash*
MT 29F 2G 08 A A A WP - xx xx xx xx ES : A
Micron Technology Design Revision (shrink)
A = 1st design revision
Single-Supply Flash
29F = Single-Supply NAND Flash Production Status
29H = High Speed NAND Blank = Production
ES = Engineering samples
Density QS = Qualification samples
1G = 1Gb MS = Mechanical samples
2G = 2Gb
4G = 4Gb Operating Temperature Range
8G = 8Gb Blank = Commercial (0°C to +70°C)
16G = 16Gb ET = Extended (–40°C to +85°C)
32G = 32Gb WT = Wireless (–25°C to +85°C)
64G = 64Gb
128G = 128Gb Block Option (Reserved for use)
256G = 256Gb Blank = Standard device
Device Width Flash Performance
08 = 8 bits Blank = Full specification
16 = 16 bits
Speed Grade (MT29H Only)
Classification 15 = 133 MT/s
12 = 166 MT/s
Mark Bit/cell Die RnB
A SLC 1 1 Package Code
B SLC 2 1 WP = 48-pin TSOP I (CPL version) (Pb-free)
C SLC 2 1 WC = 48-pin TSOP I (OCPL version) (Pb-free)
D SLC 2 2 H1 = 100-ball VFBGA (Pb-free), 12 x 18 x 1.0
E SLC 2 2 H2 = 100-ball TFBGA (Pb-free), 12 x 18 x 1.2
F SLC 4 2 HC = 63-ball VFBGA, 10.5 x 13 x 1.0
G SLC 4 2 C2 = 52-pad ULGA, 12 x 17 x 0.4 (use TBD)
J SLC 4 + 4 2 + 2 C3 = 52-pad ULGA, 12 x 17 x 0.65
K SLC 8 4 C4 = 52-pad VLGA, 12 x 17 x 1.0 (SDP/DDP/QDP)
Z SLC 1 NA C5 = 52-pad VLGA, 14 x 18 x 1.0 (SDP/DDP/QDP)
C6 = 52-pad LLGA, 14 x 18 x 1.47 (8DP, QDP, DDP)
M MLC 1 1 C7 = 48-pad LLGA, 12 x 20 x 1.47 (8DP)
N MLC 2 1 SWC = 48-pin Stacked TSOP (OCPL version) (Pb-free)
P MLC 2 1 SWP = 48-pin Stacked TSOP (CPL version) (Pb-free)
Q MLC 2 2
R MLC 2 2 Generation (M29 only)/Feature Set
T MLC 4 2 A = 1st set of device features
U MLC 4 2 B = 2nd set of device features (rev only if different than 1st set)
V MLC 4 + 4 2 + 2 C = 3rd set of device features (rev only if different)
W MLC 8 4 D = 4th set of device features (rev only if different)
Y MLC 8 4 etc.
Operating Voltage Range
A = 3.3V (2.70–3.60V), VccQ 3.3V (2.70–3.60V)
B = 1.8V (1.70–1.95V)
C = 3.3V (2.70–3.60V), VccQ 1.8V (1.70–1.95V)
*Contact Micron for help differentiating between standard and next-generation NAND offerings.
