RTL code: Register-Transfer-Level code ,通常由VHDL/verilog两种语言进行描述
Dataflow models of combinational logic describe concurrent operations on signals ,usually in a synchronous machine ,where computations are initiated at the active edges of a clock and are completed in time to be stored in a register at the next active edge. Dataflow models of synchronous machines are also referred to as RTL models, because they describe register activity in a synchronous machine. RTL models are written for a specific architecture ---that is ,the registers,datapaths,machine operations and their schedule a known a prior. --------from "Advanced Digital Design with the Verilog HDL" by Micheal D. Clietti