用VHDL实现串口控制器

本设计是实现带有接收和发送数据缓冲FIFO的UART。串口的输出只有发送和接收，没有相关的MODEM控制器的设计。整个串口控制器的的设计分为三大部分，分别为串口核心控制模块，串口发送模块和串口接收模块。核心控制模块与发送，接收模块的数据交互采用FIFO的形式，即向FIFO中送数或者从FIFO中读数即可，其他的控制线如下所示。

U1: uart_ctl 

Port map ( 

 reset => reset,--global reset ,active high

 pld_clk => pld_clk,--66MHz,local bus clock

 uart_clk =>uart_clk, --14.7546MHz extern clock, 

 --local bus signals 

 ldata => ldata,

 madd => madd,

 cs  => cs,

 rd => rd,

 irq  => irq,

 wr => wr,

 

 --UART module data control

 stopbits => stopbits,

 databits => databits,

 parityenable => parityenable,

 parityeven => parityeven,

 

 thre => thre,

 temt => temt,

 --send fifo interface

 --fifo port

 send_reset => send_reset,

 send_din => send_din,

 send_wr_en  => send_wr_en,

 send_wr_data_count => send_wr_data_count,

 send_wr_clk => send_wr_clk,

 send_full => send_full,

 send_empty => send_empty,

 send_overflow => send_overflow,

 

 --receive fifo interface

 --fifo interface

 recv_reset => recv_reset,

 recv_rd_clk => recv_rd_clk,

 recv_rd_en => recv_rd_en,

 recv_dout => recv_dout,

 recv_wr_data_count => recv_wr_data_count,

 recv_empty => recv_empty,

 recv_full => recv_full,

 recv_overflow => recv_overflow,

 --send and receive module clock

 clk16x => clk16x

 );

 

在串口核心控制模块中主要是实现主机对串口寄存器的访问，控制发送和接收模块，根据寄存器DLL和DLM实现对uart_clk的分频。

 

U2: send

port map(

 reset => send_reset,

 clk16x => clk16x,

 --transmit output

           sout => uart_tx,

 --transmit module control

           stopbits => stopbits,

 databits => databits,

 parityenable => parityenable,

 parityeven => parityeven,

 

 thre => thre,

 temt => temt,

 

 --fifo port

 din => send_din,

 wr_en  => send_wr_en,

 wr_data_count => send_wr_data_count,

 wr_clk => send_wr_clk,

 full => send_full,

 empty => send_empty,

 overflow => send_overflow);

 

发送控制模块是将FIFO里面的数据通过串口的发端发送出去，输出为thre,temt和uart_tx；

U3: uart_recv 

port map(

--global reset and clock

reset => recv_reset,

clk16x => clk16x,

--input of receive module

sin => uart_rx,

--receive module control

 

databits => databits,

parityenable => parityenable,

parityeven => parityeven,

 

--fifo interface

rd_clk => recv_rd_clk,

rd_en => recv_rd_en,

dout => recv_dout,

wr_data_count => recv_wr_data_count,

empty => recv_empty,

full => recv_full,

overflow => recv_overflow);

 

接收模块是将收到的数据安装UART的格式解析，将收到的数写到FIFO中去。