一个礼拜过去了，在实验室也用了几次FPGA还算小有成果总结如下：1安装ISE 1.1 上网申请了序列号 1.2 安装 1.3 按照以前暑假小学期的时候得书，开始学着做实验 1.4 安装ModelSim XE 1.5 上网申请XE Starter的序列号，没给我，比较郁闷 2开发板的使用 2.1 按照Quick Start所说的一步一步做，做了一个Counter 2.2 使用USB-JTAG将程序下载到片上RAM，成功运行 2.3 使用USB-JTAG将程序下载下载到PROM(xcf04s)，成功运行
3编写VGA程序 写了一个比较简单的VGA程序，让显示器显示彩条^^
4给ModelSim SE编译了Xilinx的库(其实也就用了一条命令)
5给blog进行装饰 5.1 初步装饰(日历、联系方式、播放器) 5.2 给播放器添加了playlist(写code写了我一天-_-bb)
/*********************************** VGA源代码 *****************************/
`timescale 1ns / 1ps//// Company: // Engineer: // // Create Date: 20:06:46 02/07/2007 // Design Name: // Module Name: clear // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ////module clear(clk, c, l, hs, vs); input clk; output [9:0] c; output [8:0] l; output hs; output vs; reg [9:0] c; reg [8:0] l; reg hs; reg vs;clkd2 u1 (clk,fclk);always @ (posedge fclk) begin if (c == 599) c = 0; else c = c + 1; end
always @ (posedge c[9]) if (l == 499) l = 0; else l = l + 1;
always @ (c or l) begin if (c>583 && c<600) hs = 0; else hs = 1; if (l>444 && l<450) vs = 0; else vs = 1; endendmodulemodule clkd2(clk_in, clk_out); input clk_in; output clk_out; reg clk_out; always @ (posedge clk_in) clk_out = ~clk_out;endmodule
`timescale 1ns / 1ps//// Company: // Engineer: // // Create Date: 20:24:28 02/07/2007 // Design Name: // Module Name: display // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ////module display(GRBP, hs, vs, R, G, B); input [3:1] GRBP; input hs; input vs; output R; output G; output B;assign R = GRBP[2] & hs & vs;assign G = GRBP[3] & hs & vs;assign B = GRBP[1] & hs & vs;endmodule
`timescale 1ns / 1ps//// Company: // Engineer: // // Create Date: 20:30:32 02/07/2007 // Design Name: // Module Name: color // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: //////module color(c, l, GRBX, GRBXA, GRBXB, GRBY, GRBYA);module color(c, l, GRB); input [9:0] c; input [8:0] l; output [3:1] GRB; reg [3:1] GRB;always @ (c) begin if (c<127) GRB = 3'b000; else if(c<189) GRB = 3'b111; else if(c<252) GRB = 3'b110; else if(c<314) GRB = 3'b101; else if(c<376) GRB = 3'b100; else if(c<439) GRB = 3'b011; else if(c<502) GRB = 3'b010; else if(c<564) GRB = 3'b001; else if(c<600) GRB = 3'b000; else GRB = 3'b000; end endmodule
`timescale 1ns / 1ps//// Company: // Engineer: // // Create Date: 21:01:53 02/07/2007 // Design Name: // Module Name: vga // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ////module vga(clk, R, G, B, hs, vs); input clk; output R; output G; output B; output hs; output vs; wire [9:0] cc; wire [8:0] ll; wire [3:1] RGB;//clear(clk, c, l, hs, vs);clear u1(clk,cc,ll,hs,vs);//color(c, l, GRB);color u2(cc,ll,GRB);//display(GRBP, hs, vs, R, G, B);display u3(GRB,hs,vs,R,G,B);
endmodule
